1. Field of the Invention
The present invention relates to a semiconductor storage device such as a DRAM etc. having a refresh circuit, particularly to the semiconductor storage device having a self refresh circuit for automatically refreshing memory cells while automatically counting up an internal address counter.
2. Description of the Prior Art
A DRAM (Dynamic Random Access Memory), which is one of semiconductor storage devices, is widely used as a storage device of each of various electronic apparatuses such as a personal computer and so on, because each of memory cells of the DRAM has a smaller occupying area so that the DRAM can be highly integrated. In the DRAM, however, the electric charge stored in each of the memory cells decreases with lapse of time. If the DRAM is merely left after data has been stored in the memory cell, the stored data is to disappear after all.
In the DRAM, therefore, in order to prevent the disappearance of the stored data, refresh (rewrite), which is such an action as to re-inject the electrical charge into the memory cell, is suitably performed. As the above-mentioned refresh, there has been widely used self refresh, in which a signal for requesting the refresh is generated within the DRAM while the memory cells are automatically refreshed in turn using the address activated by an internal address counter. Hereinafter, there will be described an example of a method of performing self refresh for an ordinary DRAM. FIG. 9 is a block diagram showing a self refresh circuit and other circuits relating thereto in a conventional DRAM. FIG. 10 is a timing chart showing the changes of signals with lapse of time during the self refresh process of the DRAM.
As shown in FIG. 9, the DRAM is provided with a self refresh circuit which is substantially composed of a self-in timer 1, a self refresh timer 2 and an internal address counter 3, a raw system control circuit 4, and memory cells 5 (memory array).
In FIG. 9 or 10, the ext. ZRAS signal is a raw address strobe signal while the ext. ZCAS signal is a column address strobe signal, the both signals being external input signals. On the other hand, the ZCBR signal, the ZSELFS signal, the ZREFS signal, the int. ZRAS signal, the REFA signal and the Q signal are internal signals. Among the above-mentioned signals, the signal which includes the letter xe2x80x9cZxe2x80x9d in its symbol, is L-active (low-active). The ZCBR signal becomes L (low-level), when the ext. ZRAS signal has become L after the ext. ZCAS signal became L.
The self-in timer 1 is such a circuit as to cause the ZSELFS signal to become L when the constant time tO has passed after the self-in timer 1 received the ZCBR signal, the ZSELFS signal being outputted to the output node (ZSELFS node). The self refresh timer 2 which is connected to the self-in timer 1 through the ZSELFS node, is such a circuit as to cause the int. ZKAS signal to become L at constant periodical time after receiving the L of the ZSELFS signal, and to cause the REFA signal to generate H (high-level) pulses. The internal address counter 3 is such a circuit as to count up the Q signal while receiving H pulses of the REFA signal outputted from the self refresh timer 2, so as to output it to the output node (Q node).
The Q signal is an internal address signal having a plurality of bits, namely a signal for designating the address of each of the memory cells 5 (memory array) to be self-refreshed. The raw system control circuit 4 is such a circuit as to activate (refresh) and control each of the memory cells 5 connected to the raw system control circuit 4 while receiving the int. ZRAS signal outputted from the self refresh timer 2 and the Q signal outputted from the internal address counter 3.
Hereinafter, the action of the self refresh circuit shown in FIG. 9 will be described using the timing chart shown in FIG. 10. At first, both of the ext. ZRAS and ext. ZCAS signals are H (high-level). Next, when the ext. ZRAS signal has become L after the ext. ZCAS signal became L (low-level), the ZCBR signal becomes L. The self-in timer 1 receives the L of the ZCBR signal so as to be activated. If both of the ext. ZRAS and ext. ZCAS signals hold the L states for the constant time tO after the activation (falling) of the ZCBR signal, the ZSELFS signal becomes L so that the self refresh starts.
The ZSELFS signal activates the self refresh timer 2 so as to cause the ZREFS signal to become L at the constant periodical time tB. Following that, the int. ZRAS signal becomes L. Then the H pulse is generated in the REFA signal when the int. ZRAS signal becomes L, so that the internal address counter 3 receives the pulse so as to be activated. In consequence, the Q signal (internal address) counts up one by one. The raw system control circuit 4 receives the int. ZRAS signal outputted from the self refresh timer 2 and the Q signal (internal address) outputted from the internal address counter 3 so as to be activated, so that the memory cell 5 (memory array) is refreshed. When the constant time tA has passed after the int. ZRAS signal became L, the ZREFS signal becomes H so that the int. ZRAS signal also becomes H in accordance with the H of the ZREFS signal.
As described above, during the period that the ZSELFS signal is being L, the above-mentioned actions that the ZREFS signal and the int. ZRAS signal change from H to L or from L to H are repeated so that the DRAM is automatically refreshed.
By the way, the DRAM is subjected to various tests for testing whether the self refresh will be correctly performed as previously designed or not, or the like. When the above-mentioned tests are performed, it may be the best to detect the internal signal for provoking the refresh, namely the wave form of the int. ZRAS signal so as to monitor the wave form. In the conventional circuit construction of the DRAM, however, it is impossible to detect the wave form of the int. ZRAS signal generated within the DRAM. In short, in the conventional DRAM, there exists such a problem that the int. ZRAS signal for provoking the refresh can not be monitored.
In the Japanese Laid-open Patent Publication No. 6-236682, there is disclosed a storage device (DRAM) in which a signal from which the periodical time of refresh can be detected, is outputted from an I/O pin by applying a test signal xcfx86 TEST to a section for generating a signal to un-activate a CAS system or by applying the test signal xcfx86 TEST to an output circuit, during the test mode process. In the conventional storage device, however, the wave form of the ant. ZRAS signal for provoking the refresh can not be monitored.
In the Japanese Laid-open Patent Publication No. 2-105389, there is further disclosed a dynamic type of storage device (DRAM) in which the number of refresh is counted by an internal address counter during the self refresh process so that the average value of the periodical time of the refresh is calculated on the basis of the number of the refresh and the time required for performing the self refresh. In the conventional dynamic type of storage device, however, the wave form of the int. ZRAS signal for provoking the refresh can not be also monitored.
The present invention is achieved to solve the above-mentioned problems, and has an object to provide a semiconductor storage device which can detect the wave form of the internal signal for provoking the refresh so as to monitor the wave form.
According to the present invention which has been developed to achieve the above-mentioned object, there is provided a semiconductor storage device (e.g. DRAM) in which each of memory cells (or memory array) is subjected to self refresh on the basis of a specific internal signal (e.g. int. ZRAS signal) for provoking a refreshing action (i.e. rewriting action), which includes a refresh monitor circuit appended to an output circuit. The refresh monitor circuit receives a test mode signal of H (high-level) or L (low-level) and then outputs a monitoring signal into a data output pin (or data output node) when the test mode signal is H during the self refresh process. Hereupon, the monitoring signal has a wave form as same as that of the specific internal signal.
In the semiconductor storage device, if the test mode signal applied to the refresh monitor circuit is set to H during the self refresh process, the monitoring signal having the wave form as same as that of the internal signal for provoking the refresh is outputted to the data output pin. Therefore, by setting the test mode signal to H during the self refresh process, the wave form of the internal signal for provoking the refresh can be detected at any time so that it can be monitored. In consequence, various tests relating to the self refresh, such as a test for testing whether the semiconductor storage device has a self-refreshing function as previously designed or not, can be performed easily and correctly.
In the above-mentioned semiconductor storage device, the output circuit may include a P-channel field effect transistor into which a first data signal is inputted through a gate thereof and an N-channel field effect transistor into which a second data signal is inputted, through a gate thereof, the output circuit having such a circuit construction that drains of the both field effect transistors are connected to each other, and further a source of the P-channel field effect transistor is connected to a higher voltage section (e.g. power source) while a source of the N-channel field effect transistor is connected to a lower voltage section (e.g. ground). Hereupon, the refresh monitor circuit may include a P-channel field effect transistor for monitoring use and an N-channel field effect transistor for monitoring use, the P and N channel effect transistors for monitoring use being connected to the P-channel field effect transistor and the N-channel field effect transistor in parallel, respectively. The semiconductor storage device may further include a logic circuit which receives the test mode signal and the specific internal signal, and then causes each of the field effect transistors for monitoring use to output an output signal to the data output pin when the test mode signal is H during the self refresh process while causing each of the field effect transistors for monitoring use to become a high impedance state when the test mode signal is L, the output signal having a wave form as same as that of the specific internal signal.
In this case, although the semiconductor storage device has such a simple construction that the P-channel field effect transistor for monitoring use, the N-channel field effect transistor for monitoring use and the logic circuit are merely appended to the output circuit, the wave form of the internal signal for provoking the refreshing action can be detected and monitored at any time by setting the test mode signal to H during the self refresh process. In consequence, the cost for manufacturing the semiconductor storage device may be lowered because the construction of the refresh monitor circuit becomes simple.
The above-mentioned semiconductor storage device may include a test mode signal generating circuit for generating the test mode signal of H or L on the basis of an external input signal, the test mode signal being inputted into the refresh monitor circuit.
In this case, the test mode signal inputted into the refresh monitor circuit may be easily changed to H or, L by applying a predetermined external input signal to the test mode signal generating circuit. In consequence, various tests relating to the self refresh may be more easily performed.
In the above-mentioned semiconductor storage device, the test mode signal generating circuit may cause the test mode signal to become H, when an L-active external raw address strobe signal (ext. ZRAS signal) has become L later in comparison with an L-active external column address strobe signal (ext. ZCAS signal) and an L-active external write enable signal (ext. ZWE signal).
In this case, it may be surely prevented that the test mode signal becomes H when the refresh can not be performed (ext. ZWE signal being H) because the test mode signal becomes H after the ext. ZWE signal has become L. In consequence, the accuracy of each of the various tests relating to the self refresh may be improved.
In the above-mentioned semiconductor storage device, the self refresh may be performed when a predetermined time has passed after the ext. ZRAS signal became L later in comparison with the ext. ZCAS signal.
In this case, the refresh may start after the semiconductor storage device has surely become such a state that the self refresh can be performed, because the self refresh is performed when the predetermined time has passed after the ext. ZRAS signal became L. In consequence, the reliability of the semiconductor storage device may be improved.
In the above-mentioned semiconductor storage device, the self refresh may be performed when the ext. ZRAS signal has become L later in comparison with the ext. ZCAS signal.
In this case, the time required for performing the self refresh may be shortened, because the self refresh is performed when the ext. ZRAS signal has become L. In addition, the number of the timers may be reduced by one in comparison with the case of the semiconductor storage device described above. In consequence, the functional performance of the semiconductor storage device may be improved.